The present invention relates, in general, to systems transmitting/receiving data and, more specifically, to a system and method for encoding/decoding of data to reduce coherent signal interference.
Use of radio frequency as a data communications link in interrogation/identification (I/I) systems is well known. U.S. Pat. No. 5,491,482 describes coded objects, such as bank credit cards, employee identification (ID) badges, coded tags and the like, that may be read on-the-fly from some feet away by an interrogator/reader (I/R). Portions of the description of the I/I system in the patent are included below.
Referring to FIG. 1, there is shown I/I system 10 including one or more I/R units 12, one or more badges 14, respective transmit and receive antennas 18 and 19, and a central computer 22. I/R units 12 operate at a suitable radio frequency or microwave frequency (e.g. 915 MHz or 5.8 GHz) and transmit microwave (radio frequency) beams 16. Badges 14 (which uniquely identify individual employees) are internally powered and are interrogated by respective beams 16 transmitted from directional antennas 18 of I/R units 12 positioned at selected locations. Each I/R unit 12 has a receiving antenna 19 which is closely similar to transmitting antenna 18. I/R units 12 are connected via respective cables 20 to a desktop computer 22. In the course of being interrogated via microwave beam 16 from I/R unit 12, a badge or badges 14 reply electronically by reflecting a portion of the same beam 16 back to receiving antenna 19 of I/R unit 12. Badges 14 thus uniquely identify themselves in accordance with their respectively coded and electronically stored ID numbers.
Each badge may be coded with any one of over 60 billion different numbers. By way of example, five or so different badges 14 may at one time be interrogated and identified (when in range of detection) by a respective I/R unit 12 in less than 20 milliseconds. As soon as badge 14 has been identified, its electronic circuit is put into an inactive or xe2x80x9cpower downxe2x80x9d state, so that badge 14 does not continue to respond to I/R unit 12 for as long as that badge (once it has been identified) remains within range of the respective beam 16. Once badge 14 is moved out of range of beam 16, the electronic circuit of badge 14 automatically returns to a quiescent state drawing negligible current from its internal power source. But even in quiescent state, badge 14 has sufficient input sensitivity so that the badge remains able to detect and respond to very low power density levels of beam 16. By way of example, the power density of beam 16 immediately in front of transmitting antenna 18 of I/R unit 12 is only about 0.3 mW/cm2, which is one-tenth the level set by health and safety standards. The power density of beam 16 at the location of badge 14 is substantially lower.
A typical badge includes a badge-integrated-circuit (BIC), an antenna, and a very thin battery placed on a small, insulated PC board. The BIC may be entirely implemented in complementary metal oxide semiconductor (CMOS) technology, as a single IC chip. The thickness of the badge is only slightly greater than the thickness of the battery. For example, the battery may be a lithium battery having a thickness of about 30 mils, a rating of 3 volts and a capacity of 50 mA-hr. The average current drain of the BIC is less then 1 microampere, and the service life of the battery is effectively its shelf life (e.g., four years or more).
Referring now to FIG. 2, there is shown a simplified schematic diagram of I/I system 10. This system includes I/R unit 12 with its beam 16, transmission antenna 18, receiving antenna 19, BIC 30, antenna 32 and battery 34. Beam 16 is received by antenna 32 and a RF voltage is applied as an input signal to terminal 42 of BIC 30. The positive terminal of battery 34 is connected to lead 48 which is coupled to a terminal +VDD and the negative terminal of battery 34 is connected to lead 49 which is coupled to a reference terminal (REF) shown coupled to ground potential. The circuitry of the BIC includes detector/demodulator block 50, a reset/wake-up block 52, a control/logic, data memory and data registers block 54, and modulator 56.
Incoming coded signals (described in detail in U.S. Pat. No. 5,491,482) on beam 16 are detected and demodulated in block 50, which is always turned on. Other portions of BIC 30, when not in range of beam 16, are turned off. When a xe2x80x9cresetxe2x80x9d instruction from I/R unit 12 is detected and demodulated by block 50, block 50 applies a xe2x80x9cresetxe2x80x9d data word via path 60 to reset/wake-up block 52, which in turn applies a power-on signal via path 62 to the control/logic, data memory and data registers block 54. Bit data and clock signals from block 50 are applied, via paths 64 and 66, to block 54 in response to the instructions and coded words being received by BIC 30 from I/R unit 12.
By way of example, an identifying number for an employee to which a particular badge 14 is assigned is in the form of six 6-bit words stored in six memory registers (identified as A through F) in block 54 of BIC 30. To identify this 36-bit number, I/R unit 12 interrogates each badge 14 word by word. BIC 30, by operation of its modulator block 56, via path 69, then replies to I/R unit 12 at appropriate intervals, until badge 14 has completely identified itself. This iterative procedure is described in detail in U.S. Pat. No. 5,491,482.
The I/R unit transmits to the tags at a suitable frequency a stream of binary bits of instruction and data words, and receives responses from each tag. Each of the tags has circuitry for storing, as digital bits, an identifying code number. The circuitry of each tag detects and demodulates the incoming bit stream from the I/R unit, and generates clock and timing signals slaved to the bit stream, thereby framing the incoming digital words. The circuitry has logic for responding internally to the instruction and data words of the bit stream and for responding externally to the I/R unit at selected times such that the code number of a tag is uniquely identified and that tag alone among many communicates solely with the I/R unit when so identified.
Several steps are necessary before a tag is uniquely identified. A first step includes transmitting a bit stream of instruction and data words to each and all tags present to determine the presence of at least one tag. A next step is sequentially sorting through all possible combinations of values of the plurality of coded words stored in each and all tags. A next step is tabulating the matches found between transmitted and stored words of each and all tags and responding by the tag when a match is found. A next step is determining that at least one tag has matches with all of its stored words; and a next step is transmitting instruction and data words to the tags to sort out all possible combinations of matched words in all of the tags which have responded. A last step is responding by the tags one-by-one when each is uniquely identified.
The tag described in U.S. Pat. No. 5,491,482 independently generates an internal clock signal that bears no relationship to the I/R transmitted carrier signal. Other conventional I/I systems, however, generate an internal clock signal from the I/R transmitted carrier signal. For example, each tag (or card) in I/I system 10 may generate its own clock signal 66 from the I/R transmitted carrier signal, by dividing the carrier signal from I/R 12 by a fixed number. When each tag generates its internal clock signal from the interrogator""s carrier signal, the tag""s internal clock signal is xe2x80x9ccoherentxe2x80x9d with the carrier signal. Since a plurality of tags may concurrently be interrogated by an I/R, the coherent signals may interfere with each other.
The problem of coherent signal interference is explained by reference to FIGS. 3(a)-(f) and 4(a)-(f). The figures illustrate various waveforms, labeled 80-85. First waveform 80 is the common clock signal (interrogator""s carrier). Waveforms 81 and 82 are the internally generated clock signals, clock A and clock B in tags A and B, respectively. Clock A or clock B may be output on path 66 from block 50, as shown in FIG. 2. Each tag in the I/I system may generate its clock signal by dividing the common interrogator""s carrier signal by a predetermined number. In the example shown in FIGS. 3 and 4, the predetermined number is 2.
Although not shown, it will be understood that each tag responds with a data stream of logical ONEs and ZEROs. The bit time period of each logical ONE or ZERO typically is longer than a clock cycle. For example, there may be 36 clock cycles within a bit time period. In FIGS. 3 and 4, for example, the duration of a bit time period is longer than the duration of all the combined clock pulses shown in each figure.
Depending on tolerance variations among tags, each tag may start a division of the carrier signal at a different time. For example, in FIG. 3 clock A of tag A and clock B of tag B are in phase. In FIG. 4, however, clock A and clock B are out of phase.
A tag may generate a response produced by block 54 (FIG. 2) by on/off key modulation for a predetermined number of clock periods. The responses from tag A and tag B are designated 83 and 84, respectively. As previously stated, tag A response 83 and tag B response 84 are actually the clock modulations within one bit time period. As the response signals propagate toward the I/R, the signals interfere with each other. When the response signals are in phase, as shown in FIG. 3, the response signals combine to produce a strong signal, depicted as result 85. When the response signals are out of phase, however, the result is shown in FIG. 4 and the I/R does not receive any signal.
Thus, when several tags respond concurrently to an interrogator""s query, coherent signal interference exists. Depending on the phase shifts among the response signals from the tags, the resulting signal received by the I/R varies in amplitude. In some cases, the amplitude may approach zero and detection by the I/R is impossible. While it is possible to develop algorithms to prevent concurrent responses from several cards, these algorithms are slow and become even slower as the number of tags increase in the entire tag population (address space).
The problem of coherent signal interference shows that a need exists to provide an apparatus and method for reducing the signal interference among coherent signals.
The present invention provides an apparatus for reducing coherent signal interference between at least two bit streams framed with a common clock signal. The apparatus generates a local clock signal from the common clock signal and includes a Manchester encoder for encoding the clock signal with a unique signature. Also included is a logic AND-gate for combining one bit stream of the two bit streams with the encoded clock signal to produce an encoded output signal. When the encoded output signal is combined with another of the two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end.
The exemplary encoder includes a re-circulating shift register having a serial output, a serial input, a parallel input and a clock input. The serial output of the shift register is fed back to the serial input. The clock signal is provided to the clock input of the shift register and the unique signature is provided to the parallel input. An exclusive-OR circuit combines the serial output signal of the shift register and the clock signal to produce the encoded clock signal. The unique signature is a user selected bit pattern, and it is unique to each tag in the tag population and is loaded into the parallel input of the shift register once during initialization. The shift register has a length equal to a length of the user selected bit pattern, and the bit pattern is re-circulated once for every bit time period. The bit time period is defined as n=F/DP, where F is a frequency of the clock signal in Hz, and DP is the bit rate of the bit stream in bits per second.
In another embodiment, a discriminator circuit is disclosed for decoding a bit stream containing ONEs and ZEROs, each ONE or ZERO having a bit time period. The discriminator circuit receives the bit stream, where the bit stream includes pulses framed with a common clock signal, and a local clock signal generated from the common clock signal. A first counter receives the bit stream and is clocked by the clock signal. The first counter determines that a ONE is present in the bit stream when at least one pulse is detected during a bit time period. A second counter receives the bit stream and is clocked by the clock signal. The second counter determines that a ZERO is present when no pulses are detected during the bit time period.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.